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A 0.35μm CMOS 1.9mA VCO-Core with Off-Chip Inductance on LTCC for System-in-a-Package Solu

A 0.35?m CMOS 1.9mA VCO-Core with Off-Chip Inductance on LTCC for System-in-a-Package Solutions of a 5-GHz-WLAN Transceiver
S. Mecking1 , P. Mayr1 , W. Debski2 , S. Walter2 , R. Matz2 , U. Langmann1
Bochum, Integrierte Schaltungen, Germany Mailing Address: Universit¨ tsstr. 150, Ruhr-Universit¨ t Bochum, D - 44780 Bochum, Germany a a Phone: +49-234-3226524, Fax: +49-234-3214102, E-mail: 2 Siemens A.G., Corporate Technology, M¨ nchen, Germany u
Abstract—This paper presents a 5-GHz-Band VCO designed for System-in-a-package (SiP) usage. The VCO consists of a CMOS-core and was designed and optimized concerning phase noise, current consumption and tuning-range by exploiting the potential of SiP-mounting. The measurement results as well as the theoretical background are presented. The chips were fabricated in a 0.35 ?m BiCMOS-technology and operate at a supply voltage of 2.7 V. Keywords— VCO, LTCC, WLAN, System-in-package (SiP), 5-GHz-band, phase noise, power consumption
1 Ruhr-Universit¨ t a



V Tune



I. I NTRODUCTION Until recently System-on-Chip (SoC) approaches seemed to be the best choice for building RFTransceiver-Systems. By now, the trend to System-ina-Package (SiP) solutions is becoming more and more apparent, however [1]. The main reasons are as follows: ? Chips fabricated in different technologies can easily be combined, thus providing more ?exibility. ? Narrowband passive ?lters can be implemented in the packaging (ceramics) substrate. ? High quality-factor (Q) inductors and capacitors are available. ? Inductors or passive structures which occupy large areas are cheaper on ceramics than on silicon. ? Even when using SoC, some kind of packaging is needed to connect SAW-Filters, other components or the antenna. Three different types of Multi-Chip-Module Technologies (MCM) are available for an SiP [2]. MCM-D is a ?ne resolution technology. The layers are sequentially Deposited and structered by lithography. A cheaper solution is the MCM-C technique. Several layers of Ceramics are co?red. The minimum structure size is limited to roughly 50 ?m. MCM-L is a low cost solution and closely related to printed wire board
Fig. 1. VCO schematic with CMOS-core

(PWB) Technologies. Organic layers like epoxy glass are Laminated and the minimum feature size is about 100 ?m. Regarding the VCO, obvious performance advantages result from the SiP approach: The phase noise and the current consumption for a VCO in a predetermined chip technology can signi?cantly be lowered, as described later. This paper is organized as follows: At ?rst a short overview of the pros and cons of SoC- and SiPsolutions concerning VCOs is given. After that the VCO design is presented followed by simulation and measurement results. In the last section the designed VCOs are compared to recently published oscillators. II. VCO: S I P VS . S O C A PPROACH Using an SiP approach for VCO designs offers performance bene?ts. This is due to the higher tank quality-factor, which is composed of the high qualityfactor QL of an external inductor on the ceramics sub-


III. VCO D ESIGN FOR S I P A PPROACH This work started with the design of a conventional fully integrated bipolar VCO in BiCMOS technology (CMOS: Lmin =0.35 ?m, Bip: ft =72 GHz). In a ?rst step we replaced the on-chip inductor by an external coil and in a second step the bipolar VCO-core by a CMOS core, while maintaining the bipolar current mirror and the buffer. As expected the performance concerning phase noise and current consumption was increased with each step. The design of the VCO with the best performance, namely the SiP CMOS-core VCO, is described below. The frequency-range of the VCO was chosen from 4,5GHz to 4,9GHz to ?t the demands of a sliding-IFarchitecture for 5-GHz-band-VCOs [4]. The main advantage of such an architecture is that only one frequency synthesizer is needed to realize a heterodyne down-conversion. The VCO-core consists of 0.35?m MOSFETs: a cross-coupled NMOS-NIC, an NMOS- and a PMOSvaractor for differential tuning (cf. [5]), as illustrated in Fig. 1. The chip is mounted by ?ip-chip technique on an LTCC substrate. Fig. 2 shows the LTCC-board with connectors for measurement. A. Inductor The LTCC-substrate carries the inductor, which only consists of a single turn coil. Single turn inductors are usually not suited for integrated VCOs or VCOs for frequencies lower than 5 GHz, because of their large area consumption. In addition the quality-factor of a multi-turn inductor can even increase with the number of turns n, because for higher n the inductance L increases more rapidly than series resistance R [5]. For an MCM-C technology, however, a single turn coil is the best choise for the external inductor because of 1) the limited metal line pitch, 2) the large metal height, 3) the big catch-pad size and 4) the large ceramics layer thickness. As a result, a symmetric coil without vias, realized by a low-loss metal conductor on a very low-loss ceramic substrate yields a high qualityfactor. Because of the 5-GHz-frequency-band the inductance value and therefore the occupied area of the coil are small enough to be realized easily on LTCC, where the cost-per-area is far below the costs of silicon area. Another advantage of a single turn coil is, that it can be modeled more accurately. In this work a distributed network was extracted from the layout data, to achieve a precise model with broadband qualities [6]. Thus the frequency requirements were already met by the ?rst fabricated device.

Fig. 2. Photo of ?ip-chip mounted VCO on LTCC ceramics

strate and the quality-factor QC of the attached capacitances. The phase noise equation of Leeson or modi?ed versions, like Eq. (1), clarify this dependency [3]:

L (?ω) =
F·k·T 2·Psig

· 1+

ωc 2·Qtank ·?ω


vV (1 + ωcorner ) + π ( K?ωm ), (1) ?ω 2 2

where Psig is the signal power, Qtank is the loaded quality-factor of the tank, F is the device noise factor, ωc is the oscillation frequency, and ?ω is the offset frequency at which the phase noise is calculated. While integrated inductors usually have Q-factors lower than 15 at 5 GHz (for conventional technologies) or up to 30 (for special technologies), inductors on ceramics can achieve values of about 80 at that frequency. To accomplish a fair comparison of SiP and SoC VCOs, it is important to carefully check the problems and properties that result from applying an external inductor to the sensitive varactor node of the integrated VCO part: ? In contrast to integrated VCOs with low QL , the varactor must be particularly optimized: QL is very high, so that QC becomes the limiting factor concerning the quality of the whole tank. ? ESD devices are needed at the sensitive node, in order to connect an external inductor. They will lower the Q-factor of the tank. ? The connection to the inductor (pads and ?ip-chip balls) must be accurately modeled, because of their parasitics which can put the VCO out of tune and degrade the phase noise. ? Minimum feature size on ceramics is limited. ? Underpaths in LTCC (with 60+ ?m hight of vias) will degrade the symmetry and QL . The VCO design considering these properties is presented in the next section.



In order to exploit the full potential of the SiP approach, a special focus during the design was set on all capacitances connected to the tank nodes. Because of the high Q-factor of the inductor, they become the limiting factor concerning phase noise performance, as the simple equation for the unloaded tank quality shows: 1 Qtank B. Pad choice In contrast to integrated VCOs, the phase noise in this case is de?nitely dependent of the pad-type, which is used to connect the external inductor. This is due to the quality-factor of the pad capacitances, which can lower the over-all quality-factor of the tank. In agreement with the theoretically expected results, the simulations showed that the VCO performance can be signi?cantly improved by using: 1) small pad areas, 2) large substrate-to-pad spacing, and 3) a highly doped well with a low ohmic connection to ground under the pad. (e.g. replacing a standard HF-pad with an HF-pad over an n-well increased the simulated output amplitude by up to 30 %.) As an alternative, pads above grounded metal will improve the performance, but increase the amount of not tunable capacitances. C. Varactors As for the pads, the demand of a high Q-factor applies to the varactor capacitances, as well. One important aspect while optimizing the MOS-varactor properties is to reduce its gate-resistance RG . Simulations clari?ed that RG values of just 2 Ohms can increase the phasenoise of a VCO with an external inductor. Therefore, the width W , length L and number of gate ?ngers N have to be optimized. It is important to note, that not only the sheet resistance of the polysilicon RG,poly determines RG , but also a channel component RG,ch , which is in contrast to RG,poly proportional to L/W (not to W /L), as Eq. (3)-(7) clarify [7], [8]: RG = RG,poly + RG,ch W RG,poly = · Rsheet 12 · L · N 1 1 1 = γ·( + ) RG,ch Rch,st Rch,ac
lch lch

100 80 60 40 20 0

0 2

Parameter: RG

4 6 8 10


1 1 + QL QC



1 Vtune [V]



Fig. 3. Q-factor (simulated) of varactor with varying RG

AC excitation Rch,ac . The factor γ accounts for the distributed character of RG,ch . For an ideal resistor it equals 12. η is a technology dependend parameter. Fig. 3 shows Qvar with RG as parameter. The ?gure reveals the importance of this resistance for the quality of the varactor and the tank. For simulation purpose a lumped RG is used representing the different parts described above. Even the wire resistances to the varactors should be taken into account. In addition low ohmic well- or substrate-contacts will improve the quality-factor of the varactors in the subthreshold region. D. ESD Devices In contrast to fully integrated VCO solutions, ESD devices are necessary at the oszillating node to protect the VCO core. These devices, usually realized by diodes, exhibit a limited Q-factor, which also lowers the tank quality. It is essential to consider ESD protection during the circuit design in order to meet the expected frequency range and phase noise. Special high Q ESD devices or smallest possible capacitances will help to exploit the MCM potential. IV. M EASUREMENT R ESULTS AND COMPARISON TO STATE - OF - THE - ART VCO S A phase noise of -115 to -120 dBc/Hz at 1 MHz offset, depending on the tuning-voltage, was measured at 1.9 mA VCO-core-current within the tuning range of 4.5 GHz to 4.8 GHz. The supply voltage was 2.7 V. Compared to fully integrated VCOs fabricated in standard CMOS technologies with the same min. feature size, the phase noise in relation to the current consumption was lowered. A commonly used ?gure-ofmerit (FOM) which takes phase noise and power dissipation into account is de?ned as: FOM = L (?ω) + 10 · log ?ω ωc

(3) (4) (5) L W (6) (7)



dR =

dV /ID ?

Rch,ac =

qL ηW ?Cox kT

RG,ch consists of a static component Rch,st and a component considering the channel-charge distribution for

· PVCO /mW , (8)



ACKNOWLEDGMENT We thank In?neon Technologies AG for the fabrication of the chips and the measurement support. This work was supported by the Bundesministerium f¨ r u Bildung und Forschung (BMBF), under grant number 01 M 3128 C, project INTRINSYK. R EFERENCES


phase noise [dBc/Hz]


?115 dB/Hz @ 1MHz

?120 1000 10000 100000 1e+06 1e+07

Offset Frequency [Hz]

Fig. 4. Measured phase noise of VCO with CMOS-core at 4.87 GHz output frequency

where PVCO is the power dissipation of the VCO-core. An FOM value between -181.4 dBc/Hz to -186.1 dBc/Hz, depending on the tuning voltage, could be realized. Tab. I compares the proposed VCO to recently published 5-GHz-band VCOs fabricated in more expensive technologies with smaller feature sizes or SOI technologies. Similar FOM values were achieved in this work in spite of using only a 0.35?m technology without special varactors. In addition, the silicon area occupied could be reduced by eliminating the internal inductor. This statement holds for WLAN VCOs although one or two extra pads (depending on the VCO architecture) are necessary to connect the external coil.
VCO Ref. [9] [10] [11] [11] [12] [12] This work f0 VDD [GHz] [V] 4.0 5.5 5.0 5.0 5.23 5.33 4.7 2.5 1.5 2.5 2.5 1.5 1.5 2.7 Icore Tech- Ph. Noise FOM [mA] nology [dBc/Hz] [dBc/Hz] [?m] @1MHz 7.5 0.25 -117 -176.3 4.6 0.25 -116 -182.4 2 0.25 -110 -177 2.9 0.25 -117 -182.4 1.1 0.5 -110 -182.2 SOI 11.5 0.18 -126 -188.2 1.9 0.35 -115 -181.4

V. C ONCLUSION The measurement results show, that it is possible to realize VCOs featuring both low current consumption and low phase noise values without expensive ICtechnologies by using an SiP approach. In addition, it is feasible to save up to 50 % of the chip area, compared to a fully integrated solution.

J. Ryckaert, S. Brebels, B. Come, W. Diels, D. Hauspie, S. Stoukatch, K. Vaesen, W. de Raedt, S. Donnay, “Singlepackage 5GHz WLAN RF Module with Embedded Patch Antenna and 20dBm Power Ampli?er”, IEEE International Microwave Symposium (IMS), Digest, Philadelphia, pp. 10371040, June 2003. [2] S. Donnay, P. Pieters, K. Vaesen, W. Diels, p. Wambacq, W. de Raedt, E. Beyne, M. Engels, I. Bolsens, “Chip-Package Codesign of a Low-Power 5-GHz RF Front End”, Proceedings of the IEEE, Vol. 88, No. 10, pp. 1583-1597, October 2000. [3] M. Rachedine, D. Kaczman, A. Das, M. Shah, J. Mondal, C. Shurboff, “Performance Review of Integrated CMOS VCO Circuits for Wireless Communications”, IEEE Radio Frequency Integrated Circuits Symposium 2003, Digest of Papers, pp. 77-80, 2003. [4] H. Samavati, H. R. Rategh, T. H. Lee, “A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver”, International SolidState Circuits Conference ISSCC 2002, Digest of Technical Papers, pp. 208-209, 2002. [5] M. Tiebout, “Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 7, pp. 1018-1024, July 2001. [6] G. Grau, “Verfahren zur Modellierung von Induktivit¨ ten”, a German Patent (pending), Publication number: DE 0010109554 A1, Publication date: 19.09.2002. April 2002. [7] X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P.R. Gray, C. Hu, “An Effective Gate Resistance Model for CMOS RF and Noise Modeling”, International Electron Device Meeting (IEDM) 1998, Technical Digest, pp. 961-964, December 1998. [8] S. Mecking, A. Korbel, E. Paparisto, U. Langmann, “A Combined RG /CF Large-Signal Extraction Methodology to Improve CMOS SPICE-Parameter Precision”, IEEE International Conference on Microelectronic Test Structures (ICMTS) 2002, Proceedings, Vol. 15, pp. 111-114, April 2002. [9] J. Maget, M. Tiebout, “In?uence of Novel MOS Varactors on the Performance of a Fully Integrated UMTS VCO in Standard 0.25-um CMOS Technology”, IEEE Journal of SolidState Circuits, Vol. 37, No. 4, pp. 953-958, July 2002. [10] C.-M. Hung, K. K. O, “A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 7, pp. 521-525, April 2002. [11] S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. Lacaita, V. Boccuzzi, “Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp. 1003-1011, August 2002. [12] T. Y. Kim, A. Adams, N. Weste, “High Performance SOI and Bulk CMOS 5GHz VCOs”, IEEE Radio Frequency Integrated Circuits Symposium 2003, Digest of Papers, pp. 93-96, 2003.




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